ARM 315瀏覽


RISC-V 雙周簡報 (2017-07-06)




The 7th RISC-V workshop will be hosted by Western Digital in Milpitas California on November 28-30, 2017.

Talks can be of two lengths (25 minutes and 12 minutes), and talk presenters are expected to also participate in the poster session to allow extended discussion. All poster presenters will give a 3-minute poster preview.

Submission Guidelines:

Submission abstracts should consist of at most two pages in pdf format, and must include the title, authors, and affiliations. Additional material can be appended to the submission that the organizers will review at their discretion. The submission website allow selection of the desired presentation format (25 minute talk, 12 minute talk, 3 minute poster preview).

Submission Website:

Important Dates:

  • Submission Deadline: September 17, 2017
  • Author Notification: October 1, 2017

Program Committee:

  • Dan Lustig, NVIDIA
  • Dave Ditzel, Esperanto Technologies
  • Dejan Vucinic, WD
  • G S Madhusudan, IIT Madras
  • Robert Mullins, University of Cambridge
  • Silviu Chiricescu, BAE Systems
  • Yungang Bao, ICT/CAS
  • Yunsup Lee, SiFive

Send questions relating to the program ([email protected])
and questions relating to conference operation to the executive director, Rick O’Connor ([email protected]).

RISC-V Linux第四版

SiFive的Palmer Dabbelt本周提交了第四版的RISC-V的Linux Patch,祝他好運~

SeL4 on SMP

Hesham最近完成了SeL4的SMP支持。他在Spike中使用了2到9個核來測試。這是他的博客和一些關于sel4 on RISC-V的介紹。



來自Bespoke Silicon Group的RISC-V文檔

UCSD的Michael B. Taylor教授所領導的Bespoke Systems Group小組整理了不少RISC-V的文檔,包括虛擬內存和協處理器接口RoCC。 此外,他們也用RISC-V做了一些很有趣的設計 。

My team recently completed a TSMC 16-nm tapeout with 5 Linux-capable Rockets and 496 RISC-V 32IM cores in a tiled manycore array. 4 Rockets connect via RoCC to the manycore array, and the 5th uses RoCC to talk to a neural network accelerator.



UltraSoC宣布成為業內首個支持RISC-V Trace功能的廠商

UltraSoC, the leading developer of embedded analytics technology, today announced that it has developed processor trace support for products based on the open source RISC-V architecture. The company has developed a specification for processor trace that will be offered for adoption by the RISC-V Foundation as part of the open source specification. In addition, UltraSoC today becomes the first ecosystem participant to offer an implementation of this functionality.

UltraSoC’s implementation of RISC-V processor trace functionality will be available in Q42017.


Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the release of its SoftConsole version 5.1, the world’s first available Windows-hosted Eclipse integrated development environment (IDE) for designs utilizing RISC-V open instruction set architectures (ISAs) such as RV32I. SoftConsole, Microsemi’s free software development environment enabling rapid production of C and C++ programming language designs for its field programmable gate arrays (FPGAs), will be showcased at the Design Automation Conference (DAC) in a presentation highlighting its open architecture, low power and development capabilities using RISC-V soft central processing unit (CPU) cores.

“With the majority of Microsemi FPGA designers utilizing a Windows platform for their development efforts, SoftConsole v5.1 not only supports our RISC-V soft CPU cores to enable designs with our highly secure and reliable FPGAs, but it can also be used for any RV32I standard ISA extensions,” said Tim Morin, director of marketing at Microsemi, who will be presenting on the subject at DAC on June 20. “This product release broadens the RISC-V ecosystem for those developing on Windows machines, and leverages our leadership position as we continue investing in this architecture to provide customers dependable, long-term roadmap support.”



很多人正在討論合并AUIPC和JALR指令(instruction fusion)來實現直接長跳轉的可能性。ARM的AArch64指令集已經使用了指令合并技術,比如,cortex-A72就有實現它。此外,這個討論串解釋了RISC-V User level 2.2 specification對支持返回地址棧(return address stack,分支預測的技術之一)的設計考量


新版RISC-V Dhrystone跑分變差

胡振波同學發現RISC-V gcc 7.1.0版本生成的代碼比6.1.0版本dhrystone跑分變差,詳見SiFive Forum & GitHub Issue




參見: Github IBM rocc-software

什么樣的JTAG Dongle可以用來Debug SiFive/Freedom/RocketChip呢?

群主答:只要有TCK/TDI/TDO/TMS就可以,要是有SRST更好。其實更重要的是你的JTAG Dongle要被openocd支持。



  • chisel3 issue 640
  • chisel3 issue 618
  • firrtl issue 448


群主答:切換到sifive freedom平臺吧,那個有點老了。


"從技術上來講,ARC的指令集設計的應該是極端的極致了,我從沒有見過這么極致的指令集,什么delay slot,zero hw loop等等那都是最基本的,還有很多特定的指令。所以把指令的密度推到了幾乎risc架構的極限。然后在硬件設計上也用到了很多奇技淫巧,幾乎把cpu設計藝術推到了極限。當然代價就是在硬件設計和驗證上付出了相當的efforts。但是在結果各項指標上我還沒見過有什么risc core的指標能夠超過arc的。



  • ARM DesignStart項目再獲升級,Cortex-M0和Cortex-M3處理器免預付授權費
  • Imagination宣布出售
  • 國產CPU廠商,杭州中天微宣布CPU IP核免費使用計劃
  • 國產操作系統RT-Thread獲融資,未來或許支持RISC-V CPU
  • 遨格芯(AGM)宣布免費開放FPGA IP授權
  • 騰訊云推出黑石ARM服務器,號稱具有更強的性能和更有競爭力的 TCO(總體擁有成本),且天然兼容移動端應用。


  • OSDT開源開發工具大會2017(也就是原HelloGCC會議)將在10月下旬在北京舉辦,話題和贊助征集已經開始。話題內容包括“面向RISCV等新硬件的基礎軟件支持”,各位不要錯過。
  • 開源經濟學研究-2017年年會邀請函
  • FPGA Kongress, 11-13 July 2017 at the NH Hotel München-Dornach, Germany: The Case for implementing a soft RISC-V core in FPGA.
  • RISC-V at HotChips, 20-22 August 2017 at Cupertino, California.
  • RISC-V at the Linley Processor Conference, 4-5 October 2017 at Santa Clara, California.
  • First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 14 October at Boston, Massachusetts, co-located with MICRO 2017.

Editor: 宋威,郭雄飛,黃柏瑋

本作品采用知識共享署名-相同方式共享 2.0 通用許可協議進行許可。